1. Field of the Invention
The present invention relates to barrier layer removal during the fabrication of microelectronic devices.
2. State of the Art
Microelectronic devices are comprised of a variety of discrete integrated circuits. These integrated circuits are generally connected to one another or to devices external to the microelectronic device by conductive traces or interconnects through which the discrete integrated circuits send or receive electronic signals.
One process used to form interconnects is known as a “damascene process”. In a typical damascene process, a photoresist material is patterned on a dielectric material and the dielectric material is etched through the photoresist material patterning to form a channel or trench. The photoresist material is then removed (typically by an oxygen plasma) and trench is then filled, usually by deposition, with a conductive material (e.g., such as copper and alloys thereof). The resulting structure is planarized, usually by a technique called chemical mechanical polish (CMP), which removes the conductive material that is not within the trench from the surface of the dielectric material, to form the interconnect. As is understood by those skilled in the art, a hole or via may be formed in the dielectric material beneath the trench with a conductive material in the via to connect the interconnection to underlying integrated circuit devices or underlying interconnections. In another damascene process, known as a “dual damascene process”, the trench and the via are substantially simultaneously filled with the conductive material with a single deposition.
As integrated circuits have become smaller and smaller, it has become necessary to use low dielectric constant (low-k) dielectric materials (i.e., dielectric materials with a dielectric constant below silicon dioxide) in the fabrication thereof in order to obtain low capacitance between the interconnects. Decreasing this capacitance between the interconnects results in several advantages, including reduced RC delay, reduced power dissipation, and reduced cross-talk between the interconnects. Low-k dielectric materials commonly used are carbon doped oxides (CDOs) or amorphous CDOs. CDOs tend to have a dielectric constant value less than 3.5, but suffer from weak mechanical properties. Therefore, planarization techniques, such as CMP, are generally not used with low-k dielectrics because the mechanical stresses from the planarization can result in damage to the low-k dielectrics during the fabrication of the interconnects.
Copper or copper-containing alloys are commonly used to form interconnects. However, copper can adversely affect the quality of microelectronic device, such as leakage current and reliability between the interconnects. As a result, a barrier layer is usually deposited between the dielectric material and the copper to act as a diffusion barrier. A typical material used for the barrier layer, particularly for copper interconnects, may include tantalum and tantalum nitride. However, tantalum containing barrier layers are not readily removed with stress-free or low-stress techniques, such as electrochemical techniques. Thus, the use of low-k dielectric and tantalum-containing barrier layers are substantially incompatible.
Therefore, it would be advantageous to develop apparatus and techniques to effectively remove barrier layer materials with a low stress removal process.